1. Field of the Invention
The present invention relates to processes for fabricating semiconductor devices; more particularly, processes for fabricating control gate lines for floating gate field effect transistors.
2. Description of the Related Art
The gate structure of a conventional floating gate field effect transistor (FET) includes a gate oxide layer provided on a substrate, a floating gate provided on the gate oxide layer, and a control gate separated from the floating gate by an inter-gate oxide layer. The control gate has conventionally been formed of a polysilicon layer or a polysilicon layer with a silicide layer overlying the polysilicon layer. The control gate is usually fabricated with a polysilicon layer adjacent to the inter-gate oxide in order to maintain the device characteristics provided by a polysilicon gate.
The desire to increase the speed and to reduce the power consumption of semiconductor devices has prompted the use of multi-layer structures, including a silicide layer overlying the polysilicon layer, to take advantage of the lower resistivity of the silicide. Several problems are associated with forming a silicide layer on a polysilicon layer. One such problem is that the doping level of the polysilicon must be low to insure that the silicide will adhere to the polysilicon. Poor adhesion results in silicide lift-off and device failure. Doping levels up to approximately 5.times.10.sup.19 cm.sup.-3 have been utilized; however, greater doping levels increase the probability of device failures beyond acceptable limits. Doping levels below 5.times.10.sup.19 cm.sup.-3 for the polysilicon layer create a large resistivity and power consumption and reduce speed. Further, since polysilicon is usually doped with an N-type dopant, in the fabrication of CMOS devices, the low doping level of the polysilicon layer allows P-type dopants (used to form the source and drain regions in P-channel devices) to neutralize, or invert, the doping (or conductivity type) of the polysilicon layer. An inversion of the conductivity of the polysilicon layer from N-type to P-type doping radically changes the threshold voltage (V.sub.t) of the device.
A further problem associated with the formation of a multi-layer control gate is that the device must be removed from the furnace tube, or vacuum chamber, after the deposition of the polysilicon layer to allow the polysilicon layer to be doped before the silicide layer is deposited. Each time the device is removed from the furnace tube one of two problems arise. The cooling of the furnace tube to insert the wafers causes the polysilicon accumulated on the tube walls to warp or break the furnace tube due to the divergent coefficients of thermal expansion of polysilicon and quartz. Alternatively, if the tube is maintained at a high temperature and the wafers are inserted into a hot tube there is a high risk of wafer oxidation, even if a flow of an inert gas is provided, which causes yield problems.
The problem of oxidation is more severe if buried contacts are formed. Buried contacts require the removal of the inter-gate oxide and the gate oxide in the region where the buried contact is to be formed. This leaves the substrate exposed and oxidation of the substrate in the buried contact region as the wafer is inserted into a hot furnace tube will ruin a die.